1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a nonvolatile semiconductor memory device in which memory cell information is latched in latch circuits and accesses are sequentially made thereto.
2. Description of the Background Art
A nonvolatile memory cell storing information in a nonvolatile manner has a stacked gate structure with a floating gate and a control gate, wherein a threshold voltage is changed according to an amount of changes accumulated in the floating gate and digital information of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is stored thereon according to a high level or a low level of the absolute value of the threshold value. Since the stored information is determined by an electric charge amount in the floating gate, and the floating gate is in an electrically floating state, information can be stored even after the power is switched off.
FIG. 14 is a circuit diagram showing a configuration of an array section of a conventional nonvolatile semiconductor memory device. In FIG. 14, this nonvolatile semiconductor device includes two memory arrays MAR and MAL. In the memory array MAR, memory cells MC are disposed in a matrix of rows and columns and also in the memory array MAL, memory cells MC are disposed in a matrix of rows and columns. In the memory array MAR, bit lines BLR are disposed corresponding to respective columns of memory cells MC, while word lines WLR are disposed corresponding to respective rows of memory cells MC. In FIG. 14, there are represented memory cells MC disposed in one row and four columns or bit lines BLR1 to BLR4 corresponding to respective columns and the word line WLR corresponding to the row.
In the memory array MAL, likewise, bit lines BLL (BLL1 to BLL4) are disposed corresponding to respective columns of memory cells MC, while word lines WLL are disposed corresponding to respective rows of memory cells MC. The bit lines BLR and BLL are disposed in a mutually corresponding manner in memory arrays MAL and MAR. Each bit line BLR is provided with a precharge transistor PR (PR1 to PR4) precharging an associated bit line BLR to a prescribed voltage level in response to a precharge instructing signal C1 or C2, while each bit line BLL is provided with a precharge transistor precharging an associated bit line BLL to a prescribed voltage level in response to a precharge instruction signal D1 or D2.
Between the memory arrays MAR and MAL, latch circuits LTH (LTH1 to LTH4) are disposed corresponding to respective pairs of bit lines BLR and BLL. Each of the latch circuits LTH1 and LTH4 includes a pair of cross-coupled P channel MOS (Insulated Gate Field Effect) transistors Q1 and Q2; and a pair of cross-connected N channel MOS transistors Q3 and Q4. The latch circuit LTH (LTH1 to LTH4) performs differential amplification of a signal on a latch node LNR (LNR1 to LNR4) and a signal on a latch node LNL (LNL1 to LNL4), and latch resultant complementary signals. Power supply nodes SP1 and SN1 of each of the odd-numbered latch circuits LTH1 and LTH3 are coupled to receive sense drive signals P1 and N1, while power supply nodes SP2 and SN2 of each of the even-numbered latch circuits LTH2 and LTH4 are coupled to receive sense drive signals P2 and N2.
Between bit lines BLR1 to BLR4 and corresponding latch circuits LTH1 to LTH4, there are disposed transfer gates XR1 to XR4 for connecting the bit lines to the corresponding latch circuits when made conductive. The odd-numbered transfer gates XR1 and XR3 becomes conductive in response to a transfer instructing signal T1, while the even-numbered transfer gates XR2 and XR4 becomes conductive in response to a transfer instructing signal T2.
Further, between bit lines BLL1 to BLL4 and corresponding latch nodes LNL1 to LNL4 of the latch circuits LTH1 to LTH4, there are disposed respective transfer gates XL1 to XL4. The odd-numbered transfer gates XL1 and XL3 becomes conductive in response to the transfer instructing signal T1, while the even-numbered transfer gates XL2 and XL4 becomes conductive in response to the transfer instructing signal T2.
In order to perform programming/erasure verification, there are provided determination transistors DTR1 to DTR4 that become conductive in response to signal potentials on the latch nodes LNR1 to LNR4 and drives a coincidence detection line 2r to the ground voltage level when conductive and further, there are provided determination transistors DTL1 to DTL4 that become conductive in response to signal potentials on the latch nodes LNL1 to LNL4 and drives a coincidence detection line 2l to the ground voltage level when being conductive. The coincidence detection lines 2r and 2l are provided with respective current detecting circuits 3r and 3l. The current detecting circuits 3r and 3l detect whether or not current flows on the respective coincidence detection lines 2r and 2l, and according to detection results, detect whether or not corresponding latch nodes LNRs and LNLs are at the same logic level. Now, description will be made of operations in data read of the nonvolatile semiconductor memory device represented in FIG. 14 with reference to a signal waveform diagram represented in FIG. 15.
It should be noted that in FIG. 15, there are presented signal waveforms of the bit lines BLR1, BLL1, BLR2 and BLL2 when a power supply voltage is 3 V and a word line WLL is selected.
In the standby state, the bit lines BLR (indicating the bit lines BLR1 to BLR4 representatively hereinafter) and BLL (indicating the bit lines BLL1 to BLL4 representatively hereinafter) are at the ground voltage level and further, the word lines WLR and WLL are also at the ground voltage level.
In a programming operation, the precharge instructing signal C1, first, is set to 1V+Vth (pr). Here, Vth (pr) indicates a threshold voltage of the precharge transistor PR (PR1 to PR4). Likewise, the precharge instructing signal D1 is set to 0.5V+Vth (pl). Here, Vth (pl) indicates a threshold voltage of the precharge transistors PL1 to PL4. In a case where 3 V is transmitted to the power supply nodes 1r and 1l, the precharge transistors PR1 and PR3 precharge the bit lines BLR1 and BLR3 to a voltage level of 1 V. On the other hand, the precharge transistors PL1 and PL3 precharge the bit lines BLL1 and BLL3 to a voltage level of 0.5 V.
In parallel to the precharge operation, sense drive signals P1 and N1 are both set to a voltage level of 0.5 V. When the sense drive signals P1 and N1 go to 0.5 V, the latch nodes LNR1, LNL1, LNR3 and LN3 are precharged to a voltage level of 0.5 V since the power supply nodes SP1 and SN1 in the latch circuits LTH1 and LTH3 both go to 0.5 V. After the precharge operation is completed, the word line WLR is driven into the selected state of a voltage of 3 V while keeping the bit lines BLR and BLL in an electrically floating state.
In the bit line BLR1, memory cell MC is put into the on state or the off state according to stored information thereof. When a threshold voltage of the memory cell MC connected to the bit line BLR1 is high, the memory cell MC maintains the off state and the bit line BLR1 maintains the precharge state even if the word line WLR is driven to 3 V. On the other hand, when a threshold voltage of the memory cell MC connected to the bit line BLR1 is low, the memory cell MC connected to the bit line BLR1 is put into the on state, a current flows from the bit line BLR1 to a source node (ground node) through the memory cell MC and a voltage level of the bit line BLR1 decreases to the ground voltage level. Contrast to the bit line BLR1, in the bit line BLR2, no precharge operation is performed, the word line WLL stays in the non-selected state and the bit line BLR2 maintains the ground voltage level.
Word line WLR is driven into the non-selected state, the bit line BLR1 is put into the electrically floating state at a voltage level corresponding to stored information of the memory cell MC. Then, the transfer instruction signal T1 is set to H level of 3 V to place the transfer gate XR1 in the on state. When the transfer gate XR1 is put into the on state, a voltage level of the latch node LNR1 changes according to stored information of the memory cell MC from the precharge voltage of 0.5 V. In parallel to activation of the transfer instruction signal T1, the sense drive signal P1 is driven to the power supply voltage of 3 V and the drive signal N1 is pulled down to the ground voltage level. Responsively, the latch circuit LTH1 performs differential amplification of the voltages on the latch nodes LNR1 and LNL1 and latches resultant signals of the differential amplification.
The latch node LNL1 is at a voltage level of the precharge voltage of 0.5 V. On the other hand, a voltage level of the latch node LNR1 changes from the precharge voltage level according to an electric charge transmitted from the bit line BLR1 and a small difference in voltage between the latch nodes LNL1 and LNR1 is differentially amplified by the latch circuit LTH1. In a case where a threshold voltage of the memory cell MC is high, the latch node LNR1 is driven to a voltage (3 V) higher than the precharge voltage of 0.5 V. On the other hand, in a case where a voltage level of the latch node LNR1 is lower than the precharge voltage of 0.5 V, the latch node LNR1 is driven to the ground voltage level in response to the sense drive signal N1. In this state, the latch circuit LTH1 latches complimentary signals resulting from the differential amplification while maintaining the drive signals P1 and N1 at 3 V and the ground voltage of 0V, respectively.
When transfer and latch operations of a data of a memory cell connected to an odd-numbered bit line are complete, then read-out (transfer latch) on a memory cell of an even-numbered bit line is performed. In this case, the precharge instructing signal C2 is set to a voltage level of 1 V+Vth (pr) and the precharge instructing signal D2 is driven to a voltage level of 0.5 V+Vth (pl). Accordingly, the bit lines BLR2 and BLL2 are precharged to 1 V and 0.5 V, respectively.
When the precharge operation is completed, the word line WLR is again driven to the selected state and when a voltage level of the bit line BLR2 changes according to stored information on a corresponding memory cell MC, the word line WLR is driven to the non-selected state and the bit line BLR2 is driven to the electrically floating state. Then, the transfer instructing signal T2 is driven to H level of 3 V, the transfer gates XR2 and XL2 are put into the on state and the bit lines BLR2 and BLL2 are coupled to the respective latch nodes LNR2 and LNL2 of the latch circuit LTH. The latch node LNL2 maintains the precharge voltage of 0.5 V, while a voltage level of the latch node LNR2 changes from the precharged voltage level according to an electric charge transmitted from the bit line BLR2. After the transfer operation, again, the sense drive signal P2 is driven from 0.5 V to 3 V in voltage level, while the sense drive signal N2 is driven from 0.5 V to the ground voltage level of 0V. Accordingly, the latch circuit LTH2 amplifies and latches a small difference in voltage between the latch nodes LNR2 and LNL2 at a high speed.
After stored information on memory cells are latched in the latch circuits LTHs (indicating latch circuits of LTH1 to LTH4 representatively hereinafter), data of the latch circuits LTHs are sequentially selected and read out in a unit of a prescribed number of bits (1 bit or a plurality of bits) according to a column select signal from a column decoder not represented.
A high speed serial access can be realized by sequentially and selectively outputting latch data of the latch circuits LTH.
The reason why data on memory cells connected to the word line WLR are transferred to the latch circuits in two steps is as follows: The latch circuits LTHs each include a cross-coupled type differential amplifier and in operation, latch nodes are charged and discharged according to the voltage levels of respective sense drive signals. In a case where the number of memory cells connected to one row is large, if latch circuits LTHs operate simultaneously and the sense drive signals P (P1 and P2) and N (N1 and N2) are charged or discharged, a large charging/discharging current (sense currents) flows, instantaneous increase occurs in consumed current, and there is a possibility of causing problems such as occurrence of power supply noise and interconnection line disconnection due to heat generation. Therefore, when latch operations of the latch circuits are controlled so as not to be effected at a time and thereby charge/discharge current in latch circuits LTHs is dispersed over time to eventually decrease an instantaneous current. This applies to the precharge transistors and further, fluctuations in voltage level caused by a leakage current in the floating state after the precharge is stopped. In the following description, in a case where the transfer operation is performed in a plural number of times, for example in two-time transfer operation, the first time transfer operation is referred to as an operation in the first phase and the second time transfer operation is referred to as an operation in the second phase. Memory cells whose data are read out in the first phase and memory cells whose data are read out in the second phase are disposed in a physically alternate manner in the row direction. Likewise, bit lines and latch circuits used in the first phase and bit lines and latch circuits used in the second phase are also disposed in a physically alternative manner in the row direction.
The latch circuits are used for automatic verification effected internally on whether or not programming/erasure operations are normally performed in addition to the purpose of temporarily storing read data.
Now, a state where a threshold voltage of a memory cell is low is defined as an erased state or a state where a data xe2x80x9c0xe2x80x9d is stored, and a state where a threshold voltage of a memory cell is high is defined as programmed state or a state where a data xe2x80x9c1xe2x80x9d is stored. An erase operation is simultaneously performed on memory cells connected to a word line WL (WLR and WLL). After the erase operation is completed, data on memory cells connected to the word line WLR are transferred to latch circuits LTHs according to the above described procedure. Since memory cells in the erased state each store a data xe2x80x9c0,xe2x80x9d all the latch nodes LNR are at L levels. Therefore, all the determination transistors DTRs (DTR1 to DTR4) each are in the off state and no current flows on the coincidence detection line 2r that has been precharged at a prescribed voltage level. The current detecting circuit 3r detects that no current flows on the coincidence detection line 2r and thereby, detects that erase of memory cells connected to a selected word line is complete. This applies for the word line WLL of the memory array MAL in a similar manner.
A write verification operation is performed in a similar manner and it is discriminated using latch data of latch circuit LTH whether or not xe2x80x9c1xe2x80x9d has been written on a selected memory cell. In this case, for example, in a case where data xe2x80x9c1xe2x80x9d are written on memory cells connected to the word line WLR, it is determined that programming operations on all selected memory cells have been complete when all the corresponding latch nodes LNRs go to xe2x80x9c1xe2x80x9d (H level). Therefore, in this case, write verification is performed using the current detecting circuit 31. This is because when programming is completed, all the nodes LNL (LNL1 to LNL4) go to xe2x80x9c0xe2x80x9d (L level) and no current flows on the coincidence detection line 21.
Therefore, when erase operations or programming operations are performed till no current flows on the coincidence detection line 2r or 2l using latch circuits LTHs, erase and programming operations can automatically be performed in the interior of the memory array.
Further, in the memory array, redundant cells for repairing a defective bit are included. A defective bit line replaced with the redundant circuit is still present in the memory array and in a verification operation, latch circuits connected to the defective bit line perform latch operations, similar to others. Therefore, in this case, determination transistors malfunction under influence of a latch circuit provided for the detective bit line, and a correct verification operation cannot be effected. Further, a memory cell on an unused redundant bit lines does not necessarily operate in a normal way, either. This is because although it is determined whether or not a redundant bit line operates in a normal way after redundancy replacement, no address is assigned on an unused redundant bit line, and it is not determined on whether or not the unused redundant bit line is correctly operated either.
Therefore, the following procedure is performed in order to ensure a correct verification operation while excluding an influence of an unused latch circuit provided for a defective bit line or an unused redundant bit line.
FIG. 16 is a block diagram schematically representing a configuration of peripheral circuitry of latch circuits LTH. In FIG. 16, gate circuits 8 and 9 are provided serially to the latch circuit LTH. The latch nodes LNL and LNR of the latch circuit LTH are connected to a forcibly setting circuit 5 through the gate circuits 8 and 9. The forcibly setting circuit 5 is provided commonly to latch circuits LTHs and the gate circuits 8 and 9 are provided to each of the latch circuits LTHs. The gate circuit 8 becomes conductive under control of the gate control circuit 7 and the gate circuit 9 becomes conductive in response to a select signal from an address decoder 6. The address decoder 6 stores addresses of unused bit lines and drives the unused bit lines sequentially to the selected state. The gate circuits 8 and 9 are provided separately from a column select gate coupled to a column select line transmitting a column select signal from a normal column decoder. Now, description will be made of operations of the circuitry represented in FIG. 16 with reference to a flow chart represented in FIG. 17.
After erase and programming operations are performed, memory cell data for verification are transferred to the latch circuit LTH. Thereafter, the forcibly setting circuit 5 is controlled to output an H level signal from the left side node thereof, and an L level signal from right side node thereof (step S1). Then, an address i of an unused address is set to 1 (step S2). The address decoder 6 decodes the unused address i to set the gate circuit 9 into the conductive state (step S3). Then, the gate control circuit 7 set the corresponding gate circuit 8 to the on state when a decoded result is firmly determined. Thereby, complementary signals from the forcibly setting circuit 5 are transferred to corresponding latch circuit LTH and the latch node LNL is forcibly set to H level, while the latch node LNR is forcibly set to L level (step S5). After the latch signals on the latch nodes LNL and LNR are forcibly set, the gate circuit 8 is set to the off state.
Then, it is determined whether or not the address i reaches the final value Nm (step S7) and when the final unused address has not been selected, the unused address i is incremented by 1 in step S8 and processing from step S3, again, is repeatedly performed. When it is determined, in step S7, that the unused address i has reached the final address Nm, then forced setting of latch signals in latch circuits for unused bit lines (a redundant bit line and a defective bit line) is completed and subsequently, a current detection is performed using the current detecting circuit 3r connected to the coincidence detection line 2r (step S9). The latch node LNR stays at L level by the forced setting circuit 5 and the determination transistor DTR stays in the off state and no influence is exerted on the current detecting operation. When failure is present and a current flows on the coincidence detection line 2r in a detection result in step S9, then a fail processing, that is an erase or programming operation, is repeatedly performed in step S11. When pass is determined in step S9, a pass processing is performed in step S10, wherein necessary operations such as an erase or programming operation for a next row are performed.
FIG. 18 is a signal waveform diagram representing forcibly setting operations for a case of 4 unused addresses present. As represented in FIG. 18, after the unused addresses AD1 to AD4 are sequentially put into the definite state and a corresponding gate circuit 9 is put into the on state by a decode signal from the address decoder 6, a gate signal from the gate control circuit 7 is driven to H level to set the gate circuit 8 into the conductive state. A signal at L level from the forcibly setting circuit 5 is transmitted to the latch nodes LNRs of the latch circuits #1 to #4 specified by the addresses AD 1 to AD4 and the latch nodes LNRs are forcibly set to L level. After the forced setting of voltage levels on the latch nodes of the latch circuits #1 to #4, a determination start signal is activated and a determination is performed on whether or not a current is present on the coincidence detection line by the current detecting circuit.
It should be appreciated that the number of unused addresses is equal to the number of redundant bit lines. A defective bit line is replaced with a redundant bit line and therefore, the sum of the number of defective bit lines and the number of unused, redundant bit lines is equal to the number of redundant bit lines originally provided.
With the forcibly setting circuit, determination on completion of erase/programming operations can be effected in a normal way even in an array configuration repairing of a redundant circuit. In a case of such a redundancy configuration, repairing of a defective bit line can be achieved by replacing with a redundant bit line and a defective bit line is set in the normally non-select state and a corresponding redundant circuit is selected, whereby an influence of the defective bit line can be precluded. In a case where a defect is present in a portion including a latch circuit LTH between transfer gates, however, the defect repairing may not be achieved only by redundancy replacement depending on the state of the defect, leading to a possibility of bringing the whole memory array into a defective state.
Now, a case where short circuit arises between latch circuits having different operating phases, as represented in FIG. 19, will be considered. That is, a case will be considered in which a resistance R exists due to a particle between the latch nodes LNL1 and LNL2 and thereby, the latch nodes LNL1 and LNL2 are short-circuited. In this case, as a signal waveform diagram represented in FIG. 20, a state is here represented in which data transfer/latch operations in the first phase are complete. In this state, the sense drive signals P1 and N1 are at voltage levels of the power supply voltage of 3.0 V and the ground voltage of 0 V, respectively. Further, a state is further considered in which the latch node LNR1 is held at the ground voltage of 0 V and the latch node LNL1 is held at the power supply voltage of 3.0 V.
In the second phase, the sense drive signals P2 and N2 are first driven from the ground voltage level to the voltage level of an intermediate voltage of 0.5 V. In this case, the latch node LNL2 receives the sense drive signal P1 through a resistance element R and a MOS transistor Q1 in the latch circuit LTH1, and a voltage level of the latch node LNL2 is raised higher than 0.5 V of the precharge voltage. When a voltage level of the latch node LNL2 rises, a voltage of the latch node LNL2 is transmitted to the sense drive signal P2 through a MOS transistor Q1 in the latch circuit LTH2 to raise a voltage level of the sense drive signal P2 since the latch circuit LTH2 effects differential amplification of a voltage difference between the latch nodes LNL2 and LNR2. The latch nodes LNL2 and LNR2 are isolated and the latch node LNR2 is held at a voltage level of the sense drive signal N2, namely a voltage level of 0.5 V even when in the latch circuit LTH2, a MOS transistor Q4 has been put into the on state. In this case, the gate and source of a MOS transistor Q3 come to be at the same voltage level and a MOS transistor Q3 maintains the off state. Therefore, the sense drive signal N2 is at a voltage level of 0.5 V.
After this precharge operation, a word line WLR is selected and a memory cell data is read out onto a corresponding bit line. Thereafter, the transfer instructing signal T2 is activated to make the transfer gates XL2 and XR2 conductive. When the transfer instructing signal T2 is activated as represented in FIG. 21, the bit line (BLL) precharged to 0.5 V of the intermediate voltage through the transfer gate XL2 is connected to the latch node LNL2, while the bit line BLR is connected to the latch node LNR2 through the transfer gate XR2.
Therefore, when a voltage level of the sense drive signal P2 is 1 V or higher and a voltage level on the latch node LNL2 is 1 V or higher, the latch node LNL2 decreases its voltage level a little by receiving an electric charge at the intermediate voltage level from the bit line BLL, while the latch node LNR2 changes its voltage by an electric charge corresponding to a stored data on the memory cell on the bit line BLR 2. As shown clearly represented in FIG. 21, however, when the voltage level of the latch node LNL2 is 1 V or higher, the voltage level is equal to or higher than the precharge level of the bit line, the latch node LNL2 is always determined to be at H level regardless of a logical value of the memory cell data, the latch node LNR2 are determined to be at L level and accordingly latch is effected by the latch circuit LTH2.
Further, in a case where a voltage level on the latch node LNL2 is close to that on the latch node LNR2, voltage levels on the latch nodes LNL2 and LNR2 do not change sufficiently, a sensing margin in the latch circuit LTH2 is small and thereby the latch circuit LTH2 malfunctions to latch an incorrect wrong data when an inverted data (a data of xe2x80x9c1xe2x80x9d) is transmitted to the latch node LNR2.
In a case where the latch node LNL1 is held at the ground voltage level, the MOS transistor Q3 of the latch circuit LTH2 is put in the on state even when the latch node LNL2 is precharged to the intermediate voltage of 0.5 V, and a current is supplied from the sense drive signal N2 to suppress decrease in voltage on the latch node LNL2.
Therefore, in a case where short-circuit arises between latch circuits of different operating phases, there arises such a problem that a latch circuit cannot perform a latch operation in a correct way. Especially when, with short-circuit due to the resistance element R, a voltage of the sense drive signal P2 further rises beyond the precharge voltage (0.5) of an intermediate voltage, a sensing operation cannot be performed in a correct way in the second phase since there is a rise in voltage level of the sense drive signal P2 applied to all the latch circuits operating in the second phase, and such a problem, accordingly, occurs that a determining operation as a whole cannot be performed in a correct way.
Further, in a case of an unused latch circuit, a determining operation is effected after voltage levels on a latch nodes are forcibly set to prescribed voltage levels by the forcibly setting circuit 5. In this case, a voltage level of a latch node LNR rises and a determination transistor DTR, is put into the on state in a determining operation even if the latch node LNR is forcibly set to L level by forcibly setting circuit 5 when the latch node LNR has, as represented in FIG. 22, a defect resistance element Z1 coupled to the power supply node. Further, in a case where a latch node LNL has a defect resistance element Z2 coupled to the ground node, the latch node LNL falls to L level after the latch node LNL is forcibly set to H level by the forcibly setting circuit 5 and the latch node LNR, accordingly, is driven to H level by the latch circuit LTH to turn the determination transistor DTR into the on state. Therefore, even in a case where potentials of the latch nodes LNR and LNL are forcibly set by the forcibly setting circuit 5 in order to prevent an influence of an unused latch circuit LTH on a determining operation from occurring, such a problem arises that a normal determination cannot be performed when there is present a defect coupled to the fixed potential, such as the defect resistance element Z1 and Z2.
It is an object of the present invention to provide a semiconductor memory device capable of performing correct determining operation while suppressing an influence of a short-circuit defect even when the short-circuit defect arises in a latch circuit section.
It is another object of the present invention to provide a semiconductor memory device capable of performing a correct determining operation with reliable repairing on a short-circuit defect.
It is a further object of the present invention to provide a nonvolatile semiconductor memory device capable of performing correct programming/erasure determining operations even when a short circuit arises between latch circuits of different operating phases.
It is a further another object of the present invention to provide a semiconductor memory device capable of performing a correct determining operation even when a fixed defect is present in a latch circuit.
A semiconductor memory device according to a first aspect of the present invention includes reverse current preventing elements provided between power supply nodes of a plurality of latch circuits and corresponding latch drive signal lines.
A semiconductor memory device according to a second aspect of the present invention includes a plurality of latch circuits provided between bit lines so as to be shared by first and second memory arrays. Each of the plurality of latch circuits has first and second latch nodes.
The semiconductor memory device according to the second aspect of the present invention further includes: a first determining circuit for determining whether or not the first latch nodes of the latch circuits are all at a first logic level; a second determining circuit for determining whether or not the second latch nodes of the plurality of latch circuits are all at a second logic level; and a plurality of inverter circuits for inverting latch states of the respective latch circuits. Activation of the first and second determining circuits or enabling of the inverter circuit and the second inverter circuit are performed by a control circuit according to whether or not the first determining circuit is available.
A semiconductor memory device according to a third aspect of the present invention includes: a plurality of latch circuits provided corresponding to bit lines and each for latching a data on a corresponding bit line; a forcibly setting circuit for setting forcibly a latch state of each of latch circuits that are unused in a normal operation, among the plurality of latch circuits; and a determining circuit determining whether or not latch nodes of the latch circuits are at the same first logic level. A forced setting of the latch circuits, the determining circuit is activated under the state where the latch circuits are each forcibly set in a prescribed state.
A semiconductor memory device according to a fourth aspect of the present invention includes: floating gate field effect transistors each driving a corresponding coincidence detection line, in response to signal potentials of corresponding latch nodes of a plurality of latch circuits for latching signals on bit lines, wherein an influence of a latch circuit with a fixed defect on a determining operation is suppressed by adjusting a threshold voltage of the floating gate field effect transistor.
With reverse current preventing elements, even when a short-circuit defect is present between the latch nodes of latch circuits of different operating phases, an electrical floating-up of the precharge voltage of a latch node can be prevented from occurring and an adverse influence on a determining operation can also be suppressed.
Further, with an inverter circuit for changing a latch state of a latch circuit, in a case where a defect is present in the memory arrays and the first determining circuit cannot be used, latch states of latch circuits are inverted by the inverter circuit and a determining operation is performed by the other determining circuit, so that a correct determining operation can be ensured, precluding an influence of the defect on determination of latch states even when a fixed defect is present.
Further, forced setting of states has been effected by the forcibly setting circuit or unused latch circuits are sequentially set to prescribed states in a forced way by the forcibly setting circuit, followed by a determining operation, so that the correct determining operation can be performed while suppressing an influence of the defect in an unused latch circuit,
Still further, a determination transistor for to driving a coincidence line includes a floating gate field effect transistor, and the floating gate field effect transistor dedicated to a defective latch circuit is programmed to be normally non-conductive, whereby a correct determining operation can be ensured while suppressing an influence of the defective latch circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.